1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a differential amplifier having a current mirror circuit which delivers an output to the load side by an electric current, for example, a high-speed operation system of a differential amplifier used as a high-speed data transfer driver.
2. Description of the Related Art
A differential amplifier is used in a wide range of fields. FIG. 1 shows a general configuration of such a differential amplifier. This differential amplifier is a combination of a differential pair with a diode-connected load and a source follower circuit, and a current mirror circuit is constituted by said combination, and the output of the differential amplifier is delivered to the load side by an electric current.
The differential pair and source follower circuit which constitutes the differential amplifier are described in the following documents.    Non-patent document 1: “Design of Analog CMOS Integrated Circuits,” Basic Edition, page 83, written by B. Razavi, translated by Tadahiro Kuroda, published by Maruzen    Non-patent document 2: “Design of Analog CMOS Integrated Circuits,” Applications Edition, page 394, written by B. Razavi, translated by Tadahiro Kuroda, published by Maruzen
In FIG. 1, a transistor 100 and a transistor 101 to which a non-inverting input and an inverting input are supplied respectively are connected to a grounding wire by a power source 102, and are connected to a source voltage VDD by transistors 103 and 105. Diode-connected transistors 103 and 105, transistor 104, transistor 106 constitute a current mirror circuit, and the transistor 104 and the transistor 106 to which a copy electric current flows in the current mirror circuit are connected to resistors 107 and 108 on the load side respectively, and the voltage applied to the resistors 107 and 108 is taken out as an output voltage.
In FIG. 1, when either an input signal VIN+ or an input signal VIN− becomes H, the voltage of a node 1 or a node 2 begins to drop from the source voltage VDD. When the electric potential of the node 1 or the node 2 becomes lower than the value obtained by subtracting a threshold voltage from the source voltage, an electric current begins to flow to the transistor 103 and the transistor 105, and this electric current flows to the side of the output resistor by the current mirror circuit, and an output voltage is generated.
However, in the circuit shown in FIG. 1, a delay time exists from the time when an input signal is on, or H to the time when an electric current flows to the transistor 103 or 105. FIG. 2 is an explanatory drawing of this delay time. In FIG. 2, when an input signal is on, or H, the voltage of the node 1 or the node 2 begins to drop, but an electric current does not flow to the transistor 103 or the transistor 105 until the value of the voltage becomes equal to or lower than the value obtained by subtracting the threshold voltage from the source voltage. Consequently, the time when the rising of the electric current on the copy side of the current mirror starts, i.e. the time when the rising of the current which flows to the transistor 104 or the transistor 106, starts is accordingly delayed, and the output voltage delayed by the same amount.
When a differential amplifier is used as a driver circuit for high-speed data transfer, this delay time becomes a serious problem. Particularly, in order to realize the transfer speed of 480 Mbps as set forth in the USB (Universal Serial Bus) 2.0 Standard, a delay time of 100 ps or so becomes a problem. Furthermore, in order to satisfy the stress test standard of USB 2.0, there is a problem in that it is difficult to use a low withholding voltage and high-speed transistor, and it is necessary to make a large electric current flow, so the size of the transistor becomes large, and the load capacity becomes large, and the delay time also becomes long.
The following documents are available as prior art concerning such a differential amplifier.
Patent document 1: Kokai (Jpn. unexamined patent publication) No. 10-209844 “Small level signal input interface circuit”
Patent document 2: Kokai (Jpn. unexamined patent publication) No. 11-127042 “Differential amplifier”
Patent document 3: Kokai (Jpn. unexamined patent publication) No. 2001-251149 “Amplifier Circuit”
Disclosed in patent document 1 is an interface circuit which improves the operation speed in an ordinary operation mode other than the IDDQ test mode which is a test method of a semiconductor integrated circuit, which reduces the number of clocked inverters in order to reduce the circuit area, and which improves the performance.
Disclosed in patent document 2 is a differential amplifier which can reduce an average consumption of electric current within a range of the whole current input by making the output electric current variable according to the level of a non-inverting input voltage.
Disclosed in patent document 3 is an amplifier circuit which has a stable mutual conductance, is not influenced by changes in surrounding temperatures or variations in process conditions during manufacturing, and can maintain stable amplification ratios and output resistance.
However, the aforesaid prior art could not solve the problem in that in a differential amplifier having a current mirror circuit shown in FIG. 1, the transistor constituting the current mirror circuit is cut off when the corresponding input voltage is L, and a delay arises in the operation.
Furthermore, there was a problem in that delay arises in the operation when, for example, a semiconductor device including a differential amplifier is implemented for USB standard data transfer, and data transfer is started when both of two input signals, VIN+ and VIN−, to the differential amplifier are in an L state.